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DTSTAMP:20211208T164508Z
LOCATION:Level 2 - Lobby
DTSTART;TZID=America/Los_Angeles:20211208T180000
DTEND;TZID=America/Los_Angeles:20211208T190000
UID:dac_DAC 2021_sess243@linklings.com
SUMMARY:Networking Reception & Work-In-Progress Poster Session
DESCRIPTION:Networking Reception, Work-in-Progress Poster\n\nDetermining t
 he Multiplicative Complexity of Boolean Functions using SAT\n\nSoeken\n\nW
 e present a constructive SAT-based algorithm to determine the multiplicati
 ve complexity of a Boolean function, i.e., the smallest number of AND gate
 s in any logic network that consists of 2-input AND gates, 2-input XOR gat
 es, and inverters. In order to speed-up solving time, we make use of sever
 al ...\n\n---------------------\nCANCELLED: RoHNAS–When Robustness M
 eets HW-Aware NAS: A Neural Architecture Search Framework with Conjoint Op
 timization for Adversarial Robustness and Hardware Efficiency of Convoluti
 onal and Capsule Networks\n\nMrazek\n\nNeural Architecture Search (NAS) al
 gorithms aim at finding high accurate Deep Neural Network (DNN) architectu
 res for a given application. However, DNNs are computationally-complex as 
 well as vulnerable to adversarial attacks. Towards this, we propose RoHNAS
 , a novel NAS framework that jointly optimi...\n\n---------------------\nF
 inding Optimal Implementations of Non-native CNOT Gates using SAT\n\nDrech
 sler\n\nQuantum computer architectures place restrictions on the availabil
 ity of quantum gates. Thus, a given quantum circuit usually needs to be tr
 ansformed to satisfy these restrictions. Existing transformation approache
 s tend to induce a significant overhead to enable the realization of CNOT 
 gates that a...\n\n---------------------\nA Coordinated GPU Overdrive Faul
 t Attack on Neural Networks\n\nKaeli\n\nGraphics processing units (GPUs) a
 re commonly used to accelerate training and inference of convolutional neu
 ral networks (CNNs). Modern GPUs can be shared by multiple users to execut
 e workloads concurrently. However, the reliability and security of shared 
 GPU computing have not been carefully evalua...\n\n---------------------\n
 GridNetOpt: Fast Full-Chip EM-Aware IR Drop Constrained Power Grid Optimiz
 ation via Deep Neural Networks\n\nLiu\n\nThis paper presents a fast full-c
 hip EM-aware IR drop constrained optimization framework, named GridNetOpt,
  for on-chip power grid networks via a data-driven and learning-based IR d
 rop modeling. The new method can naturally take advantage of differential 
 characteristics of DNN for fast sensitivity c...\n\n---------------------\
 nRTL regression test selection using Machine Learning\n\nParthasarathy, Ru
 shdi, Choudhary, Nanda, Evans...\n\nWe address the problem of minimizing t
 he validation cost of iterative changes in RTL design cycles. Our approach
  learns characteristics of both RTL code and tests during the verification
  process to generate estimated likelihoods that a test will expose a laten
 t bug introduced by incremental design m...\n\n---------------------\nStim
 ulus Truncation Method for Energy Efficient Memristor Based Neuromorphic C
 omputing\n\nDing\n\nA solution is presented for improving energy efficienc
 y and heightening the performance of neuromorphic computing systems. Speci
 fically, a pulse truncation (PT) method is proposed to reduce number of pu
 lses in every weight update. The neuromorphic computing system with the PT
  method is implemented a...\n\n---------------------\nGames, Dollars, Spli
 ts: A Game-Theoretic Analysis of Split Manufacturing\n\nGohil\n\nSplit man
 ufacturing has been proposed to prevent intellectual property (IP) piracy.
  Researchers have formulated various attacks and defenses, creating a cat-
 and-mouse game. Here, we take an orthogonal approach; rather than developi
 ng an attack or a defense, we propose a game-theoretic framework to a...\n
 \n---------------------\nGlitch and Level Detection Algorithms for Analog 
 Mixed-Signal Verification Coverage Management\n\nSanyal, Balasubramanian\n
 \nAutomatic detection of glitches and levels (steps) are important require
 ments for analog and mixed-signal (AMS) coverage management. In the absenc
 e of mature AMS verification coverage management software from the EDA ven
 dors, we propose novel methods for detecting glitches and levels in time-d
 omain ...\n\n---------------------\nTatami: Dynamic CGRA Reconfiguration f
 or Multi-Core General Purpose Processing\n\nLee, Carlson\n\nCGRAs enable e
 nergy-efficient, highly configurable solutions for embedded system workloa
 ds. Most existing techniques have been proposed in the context of single c
 ore systems and are limited to benefit multi-core configurations.\n\nTo ta
 ke advantage of multi-core systems, one needs to support dynamical...\n\n-
 --------------------\nAn Efficient Cell Capacitor Compact Modeling and App
 lication for High-speed DRAM Design\n\nKim\n\nWe propose a compact model o
 n the layout dependent AC impedance of the cell capacitor in the frequency
  range of 1k~10GHz for sub-20 nm DRAM technology node. Several layout cand
 idates are proposed for achieving high efficiency of capacitor based on ac
 curate model (>95%). Simulation results show that ...\n\n-----------------
 ----\nFASCINET: Fully Automated Single-Board Computer Generator Using a Ne
 ural Network Based Datasheet Scrubber\n\nFayazi\n\nDesigning Single-Board 
 Computers (SBCs) is becoming more challenging given the growing number of 
 discrete IPs that are made available. The procedure of deciding Peripheral
  Circuits (PC) configurations, determining their elements values is compli
 cated and time-consuming. An SBC generation tool is pro...\n\n------------
 ---------\nSpecMCTS: Accelerating Monte Carlo Tree Search using Speculativ
 e Tree Traversal\n\nKim\n\nMonte Carlo Tree Search (MCTS) algorithms show 
 great success in decision-making problems. MCTS requires significant compu
 ting loads to make a good decision. Parallelizing MCTS is challenging beca
 use MCTS is a sequential process. We present SpecMCTS, which accelerates M
 CTS by speculatively traversing...\n\n---------------------\nCANCELLED: So
 nicFFT: A system architecture for ultrasonic-based FFT acceleration\n\nSab
 ry Aly\n\nFast Fourier Transform (FFT) is an essential algorithm for numer
 ous scientific and engineering applications. It is key to implement FFT in
  a high-performance and energy-efficient manner. In this work, we leverage
  the properties of ultrasonic wave propagation in silicon for FFT computat
 ion. We introd...\n\n---------------------\nA Robust DNN Accelerator with 
 Data-path Fault Detection and Mitigation\n\nBurel\n\nDeep Neural Networks 
 are increasingly used in safety critical autonomous systems. We present a 
 DNN accelerator architecture which provides fault detection and fault tole
 rance. Our approach is based on an Output Stationary systolic architecture
  augmented with fault detection based on fast on-line fun...\n\n----------
 -----------\nOn the Impact of Electrical Masking and Timing Analysis on So
 ft Error Rate Estimation in Deep Submicron Technologies\n\nPaliaroutis, Ts
 oumanis\n\nSoft errors consist a crucial reliability concern for the Integ
 rated Circuits (ICs) as the continuous CMOS technology downscaling renders
  them vulnerable to radiation-induced hazards. Therefore, the Soft Error R
 ate (SER) evaluation comprises a necessary process to design radiation-har
 dened ICs. A SP...\n\n---------------------\nCANCELLED: IO Performance Mod
 eling for Communication Workloads\n\nKhan, Abousamra, Islam, O'Neal, Milli
 er...\n\nCommunication workloads’ pre-silicon performance on compute
  servers is not only a function of core and uncore performance, but also d
 ependent on IO performance. We present augmenting Simics functional simula
 tor with performance tools to convert core/uncore into performance models 
 enabling pre-...\n\n---------------------\nSecuring Deep Neural Networks A
 gainst Adversarial Attacks through Voltage Overscaling\n\nIslam\n\nDeep ne
 ural networks (DNNs) are shown to be vulnerable to adversarial attacks. Pr
 eviously proposed defenses against adversarial attacks require substantial
  additional overheads, making it challenging to deploy these solutions in 
 devices under power and computational resource constraints, such as emb...
 \n\n---------------------\nParameter Approximation in CNNs for Improved In
 ference on FPGA\n\nAkhlaghi\n\nIncreasing the number of parameters of Conv
 olutional Neural Networks (CNNs) to improve their accuracies causes their 
 computational and memory demands to exceed the computational and storage c
 apacities of mobile embedded devices. Here, we focus on improving the memo
 ry demands of CNNs during the infer...\n\n---------------------\nCANCELLED
 : ARGOS: an Adaptive and ReGion-scale knowledge distillation for Object re
 cognition Systems\n\nFarhadi\n\nObject recognition research communities ha
 ve achieved great success using neural networks. Reducing these networks' 
 computational cost remains a challenge, which impedes their deployment on 
 embedded devices. Recent studies employ a keyframe selection and temporal 
 knowledge distillation for detecting...\n\n---------------------\nPOSAR: A
  Flexible Posit Arithmetic Unit for RISC-V\n\nCiocirlan, Loghin, Ramapantu
 lu, Țăpuș, Teo\n\nWe present POSAR, a flexible Posit Arithm
 etic Unit that supports different operand sizes suitable for trading off a
 ccuracy for memory and energy savings. POSAR is implemented in Chisel, int
 egrated with Rocket Chip, and evaluated on an Arty A7-100T FPGA. Prelimina
 ry results show that POSAR with 16-bi...\n\n\nVirtual Program: Presented I
 n-Person
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