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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Lobby
DTSTART;TZID=America/Los_Angeles:20211208T180000
DTEND;TZID=America/Los_Angeles:20211208T190000
UID:dac_DAC 2021_sess243_WIP142@linklings.com
SUMMARY:An Efficient Cell Capacitor Compact Modeling and Application for H
 igh-speed DRAM Design
DESCRIPTION:Networking Reception, Work-in-Progress Poster\n\nAn Efficient 
 Cell Capacitor Compact Modeling and Application for High-speed DRAM Design
 \n\nKim\n\nWe propose a compact model on the layout dependent AC impedance
  of the cell capacitor in the frequency range of 1k~10GHz for sub-20 nm DR
 AM technology node. Several layout candidates are proposed for achieving h
 igh efficiency of capacitor based on accurate model (>95%). Simulation res
 ults show that optimal layout can improve effective capacitance at 1GHz up
  to 12% and equivalent series resistance by 92% compared to those of conve
 ntional layout. Power supply induced jitter and peak to peak amplitude of 
 power noise can be reduced by 56 and 54% respectively, close to those of i
 deal capacitor 67 and 65%\n\nVirtual Program: Presented In-Person
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