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DTSTART:19700308T020000
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DTSTART:19701101T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164413Z
LOCATION:Level 2 - Lobby
DTSTART;TZID=America/Los_Angeles:20211208T180000
DTEND;TZID=America/Los_Angeles:20211208T190000
UID:dac_DAC 2021_sess243_WIP147@linklings.com
SUMMARY:POSAR: A Flexible Posit Arithmetic Unit for RISC-V
DESCRIPTION:Networking Reception, Work-in-Progress Poster\n\nPOSAR: A Flex
 ible Posit Arithmetic Unit for RISC-V\n\nCiocirlan, Loghin, Ramapantulu, &
 #538;ăpuș, Teo\n\nWe present POSAR, a flexible Posit Arithmetic 
 Unit that supports different operand sizes suitable for trading off accura
 cy for memory and energy savings. POSAR is implemented in Chisel, integrat
 ed with Rocket Chip, and evaluated on an Arty A7-100T FPGA. Preliminary re
 sults show that POSAR with 16-bit operands achieves the same Top-1 accurac
 y as IEEE 754 32-bit floating-point on a Cifar-10 CNN, but with a speedup 
 of 18%. In contrast to some related works, we show that 8-bit posit is not
  suitable to replace 32-bit floating-point due to low accuracy.\n\nVirtual
  Program: Presented In-Person
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