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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164413Z
LOCATION:Level 2 - Lobby
DTSTART;TZID=America/Los_Angeles:20211208T180000
DTEND;TZID=America/Los_Angeles:20211208T190000
UID:dac_DAC 2021_sess243_WIP150@linklings.com
SUMMARY:On the Impact of Electrical Masking and Timing Analysis on Soft Er
 ror Rate Estimation in Deep Submicron Technologies
DESCRIPTION:Networking Reception, Work-in-Progress Poster\n\nOn the Impact
  of Electrical Masking and Timing Analysis on Soft Error Rate Estimation i
 n Deep Submicron Technologies\n\nPaliaroutis, Tsoumanis\n\nSoft errors con
 sist a crucial reliability concern for the Integrated Circuits (ICs) as th
 e continuous CMOS technology downscaling renders them vulnerable to radiat
 ion-induced hazards. Therefore, the Soft Error Rate (SER) evaluation compr
 ises a necessary process to design radiation-hardened ICs. A SPICE-oriente
 d electrical masking analysis, combined with a TCAD characterization proce
 ss, contributes to an accurate SER estimation. The impact of a Static Timi
 ng Analysis (STA) methodology on SER and the consideration of the actual i
 nterconnect delay are discussed. Experimental results on ISCAS ’89 benchma
 rks, synthesized with respect to 45nm and 15nm technology, indicate the SE
 R variation as the device scales down.\n\nVirtual Program: Presented In-Pe
 rson
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