BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20211208T164413Z
LOCATION:Level 2 - Lobby
DTSTART;TZID=America/Los_Angeles:20211208T180000
DTEND;TZID=America/Los_Angeles:20211208T190000
UID:dac_DAC 2021_sess244_LBR108@linklings.com
SUMMARY:Late Breaking Results: Heterogeneous Circuit Layout Centerline Ext
 raction for Mask Verification
DESCRIPTION:Late Breaking Results Poster, Networking Reception\n\nLate Bre
 aking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask
  Verification\n\nBai\n\nParasitic inductance estimation and calculation ba
 sed on the extracted centerline result play an important role in mask veri
 fication. This paper formulates the centerline extraction problem as a Vor
 onoi diagram to collect centerline points. We then present a graph-based i
 nvalid centerline removal method to generate an initial centerline result.
  Finally, complexity-driven centerline optimization is proposed to further
  optimize the centerline while considering the irregular structures and de
 sign constraints. Compared with the state-of-the-art commercial 3D-RC para
 sitic parameter extraction tool RCExplorer, experimental results show that
  our algorithm achieves a better average precision ratio of 99.8% on cente
 rline extraction while satisfying all design constraints.\n\nVirtual Progr
 am: Presented In-Person
END:VEVENT
END:VCALENDAR