BEGIN:VCALENDAR VERSION:2.0 PRODID:Linklings LLC BEGIN:VTIMEZONE TZID:America/Los_Angeles X-LIC-LOCATION:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:19700308T020000 RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:19701101T020000 RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20211208T164509Z LOCATION:Level 2 - Exhibit Hall DTSTART;TZID=America/Los_Angeles:20211206T170000 DTEND;TZID=America/Los_Angeles:20211206T180000 UID:dac_DAC 2021_sess249@linklings.com SUMMARY:Designer, IP and Embedded Systems Poster Networking Reception DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece ption\n\nCANCELLED End-to-End Solution for structured implementation of hi gh-speed data buses\n\nBehera, Agarwal, Rai, Tuteja\n\nHigh-speed buses re quire multi-stage pipeline repeater flops to travel large distance (> 10mm ) in complex SoCs (size > 200mm2). Meeting stiff performance targets (1Ghz +) on these bidirectional busses across PVT corners is highly challenging. Standard EDA tools do not offer complete solutions and req...\n\n-------- -------------\nCANCELLED: Modernizing a Nationwide Indoor/Outdoor Package Sorting System\n\nHackathorn\n\nA global logistics giant needed help when the mission critical technology it relied on for package tracking was declared “end-of-life” by̷ 9;the vendor that created it with no replacement offering. This hard ware and software system was a...\n\n---------------------\nSHIFT LE FT: NOVEL POWER ANALYSIS METHOD for LARGE-SCALE AI PROCESSORS\n\nMitra\n\n Traditional power analysis with simulation vectors lacks real scenarios, r equires a synthesized netlist and gate level vector, which is unavailable in the early stage. Shift left with the novel power analysis method, we ca n quickly iterate of power features in the early stage of the project, an alyz...\n\n---------------------\nAccurate and efficient high-performance memory modeling for full-chip power noise analysis\n\nMirza\n\nLong-establ ished methods of analyzing IR drop contribution of power-grid over RAMs ut ilize RAM models that fall in two categories. (1) Models that provide SPIC E level accuracy but require impractical amount of resources to characteri ze and to analyze large designs. (2) Models that evenly distribute ...\n\n ---------------------\nVerification Methodology for High Resolution High S peed CMOS Image Sensor SoC - Leveraging Innovations in EDA Tools\n\nVishwa karma, Agarwal\n\nCMOS Image Sensor SoCs for cinematography, broadcast, an d virtual reality applications require ultra-high resolution (>8K) and hig h frame rate (>120FPS) needing a column-parallel readout architecture with each column containing more than 10 ADCs and SRAM cells. Verification of such SoCs is extremely...\n\n---------------------\nChristmas Lights Displ ays As Embedded Systems\n\nRoberts\n\nMix a little fun into DAC. Utilize your embedded skills as a community service, to make other people happy. With just a modicum of skills and budget, you can use your microcontroller s to drive your Christmas lights (and motorized) displays. Sync your ligh ts to music, or to your own software-contr...\n\n---------------------\nIn novative Techniques to Accelerate Error Handling Verification of Complex S ystems\n\nParikh, Rajendra, Graniello\n\nError handling verification is on e of the key phases in verification and determining the reliability of any embedded system. It involves verifying that the system correctly detected and gracefully reported various errors. This is especially critical for S mart Network Interface Cards (NICs) (also kno...\n\n---------------------\ nPerformance Modeling of Digital Processing Systems\n\nChandra, Shankar\n\ nPerformance modeling of complex and large processing systems containing m ultiple processors, shared memories and multiple application threads remai n inadequate. Conventional modeling approach to predict performance early in architecture phase relies on modeling methodology utilizing languages l ike S...\n\n---------------------\nRouting layer re-optimization in Physic al Synthesis\n\nReddy\n\nPhysical Synthesis tools typically use heuristic optimization techniques to cope with ever increasing design sizes. They al so need to deal with optimizing multiple objectives such as improving timi ng, decreasing area/power, reducing congestion, and so on. In addition, th e accuracy of optimization en...\n\n---------------------\nDual Feature Ve ctor Hetero Graph Neural Network (DFV-GNN) based Post-Layout Parasitic Est imation\n\nKim\n\nParasitic and layout depended effect (LDE) are become mo re prominent for advanced node circuit. In this paper, we presented a nove l graph neural network based post-layout parasitic estimation methodology which can accurately predict both routing and individual transistor parasi tic based on pre layou...\n\n---------------------\nAccelerating advanced node ramp up and robust Design Enablement for leading edge SoC designers\n \nKwan\n\nDeveloping advanced technology nodes entails challenging process ramp up and robust design enablement. A key deterrent for yield ramp-up and EDA design enablement is the lack of quality and comprehensive layout that effectively probe process capabilities and design/process interactio n. Process e...\n\n---------------------\nPI Signoff Methods Used in a 5 nm InFO Design\n\nKim\n\nSuccess in today's electronics market place requi res highly integrated chips, at the same time, advanced process nodes crea te new challenges for integration, different advanced 3DIC (including 2.5D ) package structures are proposed.\nThere are many challenges for 3DI C PI analysis: the modeling of...\n\n---------------------\nMOVE TO VIRTUA L: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs\n\nJoseph, Rachamalla, Ghosh, Reddy, Joy...\n\nIn t he microprocessor design cycle, time spent in the hardware lab is crucial. There is a need to resolve issues seen in the hardware lab as quickly as possible. The data available from hardware is partial. Access to more expa nded data based on this partial hardware dump data helps lab debug signifi ...\n\n---------------------\nSoC Architectural Exploration for AI and ML accelerators with RISC-V\n\nHsu\n\nSoC developers and system designers are looking at hardware acceleration options for AI and Machine Learning appl ications moving from cloud-based algorithms to dedicated hardware. Since t he algorithms are already configured for multicore support the tradeoffs b ecome focused on the structure of proce...\n\n---------------------\nUpdat ing RISC-V microarchitecture in the field through Menta co-extended cores and Codasip Studio\n\nBAILI, Prikryl\n\nThis paper describes how Menta and Codasip enable customers to extend processors in systems on chip (SoC) af ter they have been manufactured.\nThe RISC-V ISA is modular and allows cus tom instructions. Codasip Studio can be used to extend a Codasip core usin g custom instructions with the necessary addi...\n\n---------------------\ nEarly Layout Area and PLS Estimation by Designers\n\nLongrigg, Symmons, C lewes, Bhargava\n\nArea estimation of IC layouts has become an important r equirement for early design and top-down chip planning tools. The relation of area and aspect ratio is necessary for layout planning. For custom ana log IPs, matching placement and routing is very important in layout\ndesig n of high-performance an...\n\n---------------------\nMulti-core System Ve rification Using Uvm Portable Stimulus​\n\nKumar\n\nThe fast-moving technological innovations have created a huge pressure on silicon requirem ents which translates to more design complexity and shrinking time to mark et. To address the need for reduction in verification cycle for complex mu lti-core designs, a scalable and portable method has been prop...\n\n----- ----------------\nRISC-V processor verification methodology with dynamic t estbench for asynchronous events\n\nWright, Lapides\n\nFor SoC designers a dopting RISC-V, tackling the processor DV tasks presents some new \nchalle nges. The established SoC flows have some standard assumptions – test benc hes written for UVM SystemVerilog flows and known good processor IP from a mainstream supplier. With the availability of open source R...\n\n------- --------------\nNew file system to automatically "spill" workloads across Datacenter and Cloud\n\nPrasad, Sinha, Ajanovic\n\nInspite of the world mi grating to the Cloud, the compute intensive industries like Semiconductor design are yet to benefit from it. Most organizations have invested in bui lding a large IT infrastructure to manage all the requirements. Since Clou d provides the latest technology and workload elasticit...\n\n------------ ---------\nCloud Infrastructure for Remote and Scalable EDA Hardware Train ing\n\nJones\n\nHerein, we describe the results of a pilot program between Notre Dame and CMC Microsystems to enable EDA tools from a cloud-based pl atform. First, we describe the initial success of an undergraduate High-Le vel Synthesis (HLS) course, where students completed their design flow on an Amazon AWS EC2 cl...\n\n---------------------\nAccelerating Standard Ce lls Variation-Aware Characterization Methodology with Machine Learning Tec hniques\n\nTan\n\nVariation-aware characterization for timing libraries (. libs) is a necessity for modern process nodes, due to the increased impact of process variability from shrinking feature size, increased device inte gration and low voltage operations. \n\nA key hurdle to producing accurate variation model timing ...\n\n---------------------\nAMS Verification of HBMPHY: Challenges & Solutions - 12nm Process Node\n\nNarawade, Mehta\n\nW e will be presenting our work done on creating AMS verification setup that uses SV-UVM testbench for HBMPHY chip in 12nm technology node. The abstra ctions used in the design, viz., RTL and transistor level (TL) based on th e design scope are discussed. In doing so, the challenges that we faced we re ...\n\n---------------------\nMethodology for early timing and floorpla nning closure in custom circuit design\n\nRamamurthy\n\nA pre-layout metho dology is disclosed that allows designers to achieve a high degree of timi ng and floorplanning closure during the early stages of custom macro circu it design. The methodology utilizes Electronic Design Automation (EDA) to ols that facilitate an efficient, iterative process of floor...\n\n------- --------------\nCANCELLED: Beyond Lint\n\nWalravens\n\nManagers often see verification as a necessary evil that consumes an outlandish portion of th e overall project effort. Any means to reduce the verification effort, the refore, should be grasped with both hands. \nFormal consistency checks are one such means. In addition to reducing effort, they can co...\n\n------- --------------\nMemory Peripheral Standard Cell Architecture Optimization using DTCO under Strong Area Restriction\n\nAhn\n\nCustom and manual desig ns have been mainstream for the memory industry for a long time.\nHowever, as the complexity of the peripheral block has increased, there has been a demand for extending automation methodology to memory designs. However, u nlike logic designs, memory designs have distinct charac...\n\n----------- ----------\nUtilizing the Cloud to Increase Library Characterization Throu ghput and Reduce Schedule Bottlenecks\n\nTan, Digraskar\n\nToday, SPICE-ba sed characterization of Liberty (.lib) models for modern standard cell lib raries involves running hundreds of millions of SPICE simulations, with th e amount of simulations needed increasing exponentially over the past few years, due to added quantity and complexity of data in .lib mod...\n\n---- -----------------\nCANCELLED: Resolution of Verification bottleneck by Fun ctional Coverage Automation\n\nKatharia, Malvi, More, Gharat\n\nThe effort s to randomize and constraints the test cases is based on the developer or verification engineers perception of test vectors required and can easily lead to the hidden bug being overlooked. Traditionally, the coverage goal s would have been reached by writing more test cases with unpredicta...\n\ n---------------------\nMOVED TO VIRTUAL: The Reality and Opportunities of Semiconductor Design on the Cloud\n\nKim, Ha, Kim, Do, Kim\n\nAdvanced pr ocess nodes, complex technology requirements and high design complexity le ad to more complicated design process than before. Also, it mandates the u se of high computing resources to be able to meet short time-to-market req uirement. In overall, the EDA design infrastructure is moving towar...\n\n ---------------------\nMOVE TO VIRTUAL: NEXA: Cloud Native Platform for Co llaborative Hardware Logic Design in Step-wise Refinement Implementation F lows\n\nJoseph, Baddam, Reddy, Pulluru, Joy...\n\nWe introduce NEXA, a ne w cloud-native EDA platform for collaborative hardware logic design and de bug. EDA tools and hardware design data co-exist as scalable, on-demand mi croservices. \nNEXA platform web applications leverage these microservices to provide new hardware design experiences like “...\n\n\nVirtual Pr ogram: Presented In-Person END:VEVENT END:VCALENDAR