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BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
DTEND;TZID=America/Los_Angeles:20211206T180000
UID:dac_DAC 2021_sess249_DESPOST101@linklings.com
SUMMARY:Innovative Techniques to Accelerate Error Handling Verification of
  Complex Systems
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nInnovative Techniques to Accelerate Error Handling Verification o
 f Complex Systems\n\nParikh, Rajendra, Graniello\n\nError handling verific
 ation is one of the key phases in verification and determining the reliabi
 lity of any embedded system. It involves verifying that the system correct
 ly detected and gracefully reported various errors. This is especially cri
 tical for Smart Network Interface Cards (NICs) (also known as Network Acce
 lerators), as they are usually located in an isolated environment and need
  to be continuously online with little human interaction. In addition, fai
 lure to report an error may result in security vulnerabilities, resulting 
 in a denial of service or other exploits. \nDue to the technology advancem
 ent in recent years, the complexity of Smart NICs has increased, resulting
  in a greater number of error scenarios. This has made the task of error h
 andling verification even more challenging using traditional constraint-ba
 sed random verification. \nWe leveraged various Formal Property Verificati
 on (FPV) techniques including back propagation, design reduction and free 
 variables to address challenges associated with key verification aspects o
 f error handling such as error detection, error reporting and graceful com
 pletion. Using these techniques, we completed the error handling verificat
 ion task for the HW Decompression Accelerator IP six weeks before the sche
 dule and with less than half the number of engineers compared to tradition
 al constraint-based random verification methodology.\n\nVirtual Program: P
 resented In-Person
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