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DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
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UID:dac_DAC 2021_sess249_DESPOST102@linklings.com
SUMMARY:CANCELLED End-to-End Solution for structured implementation of hig
 h-speed data buses
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nCANCELLED End-to-End Solution for structured implementation of hi
 gh-speed data buses\n\nBehera, Agarwal, Rai, Tuteja\n\nHigh-speed buses re
 quire multi-stage pipeline repeater flops to travel large distance (> 10mm
 ) in complex SoCs (size > 200mm2). Meeting stiff performance targets (1Ghz
 +) on these bidirectional busses across PVT corners is highly challenging.
  Standard EDA tools do not offer complete solutions and requires user inte
 rvention at various stages\n\nThis paper proposes an automated solution fo
 r structured placement of repeater flops along with a customizable clock t
 ree with minimal user intervention. The solution works in 3 stages:\n1.	In
 telligent placement of pipeline repeater flops, by assessing the distance 
 between ports and direction of data flow.\n2.	Ladder style clock tree stru
 cture provides a skew gradient across repeater flop groups.\n3.	Buses are 
 trunk routed in a controlled manner to optimize routing resources and cros
 stalk.\nThe automation helped in predictable convergence and reducing timi
 ng eco cycles.\nThis solution is independent of technology nodes and is fl
 exible & easily deployable.\n\nVirtual Program: Presented In-Person
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