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DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
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UID:dac_DAC 2021_sess249_DESPOST103@linklings.com
SUMMARY:Memory Peripheral Standard Cell Architecture Optimization using DT
 CO under Strong Area Restriction
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nMemory Peripheral Standard Cell Architecture Optimization using D
 TCO under Strong Area Restriction\n\nAhn\n\nCustom and manual designs have
  been mainstream for the memory industry for a long time.\nHowever, as the
  complexity of the peripheral block has increased, there has been a demand
  for extending automation methodology to memory designs. However, unlike l
 ogic designs, memory designs have distinct characteristics of strong area 
 constraint and harsh P&R environments. To resolve the issues, it is essent
 ial to adopt Design Technology Co-Optimization (DTCO) in the early stage. 
 \nIn this work, we optimize the architecture of standard cells used in per
 ipheral blocks. 1) We apply 4 main items to optimize cell architecture and
  layout. 2) We estimate the enhancement of P&R feasibility with key P&R fa
 ctors. 3) We analyze cell performance improvement and corresponding power 
 trade-off with SPICE simulations.\nWe provide a set of experimental data w
 ith 5 representative cells that occupy more than 50% area of the periphera
 l block. Cell area is reduced to 10%, and propagation delay, rise/fall tra
 nsition are improved up to 10%. Enhancement of auto P&R feasibility is est
 imated in terms of 7.6% utilization gain and 5.6% M2 routing track increas
 es.\nIn future work, we plan to examine actual P&R results and optimize pr
 ocesses in the earlier stage (e.g., design rules).\n\nVirtual Program: Pre
 sented In-Person
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