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DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
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UID:dac_DAC 2021_sess249_DESPOST106@linklings.com
SUMMARY:CANCELLED: Resolution of Verification bottleneck by Functional Cov
 erage Automation
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nCANCELLED: Resolution of Verification bottleneck by Functional Co
 verage Automation\n\nKatharia, Malvi, More, Gharat\n\nThe efforts to rando
 mize and constraints the test cases is based on the developer or verificat
 ion engineers perception of test vectors required and can easily lead to t
 he hidden bug being overlooked. Traditionally, the coverage goals would ha
 ve been reached by writing more test cases with unpredictable timelines (p
 articularly keeping time to market guidelines in view). Functional Coverag
 e defines critical states and Constrained Randomization tests those states
  in unpredictable ways. Often Constrained Randomization necessarily repeat
 s states or worse catastrophically misses the coverage point which has the
  “hidden” bug since the coverage points are written by the ver
 ification engineer by using coverage bins. To meet coverage goals, the ver
 ification engineer would need to write more test cases. \n\nThis presentat
 ion explores the standard Constrained Randomization techniques to attain c
 overage and uses coverage automation tools, using intelligent routines and
  algorithms, and analyzes the coverage matrix and does the maximum possibl
 e coverage by traversing the paths to detect undetectable bugs to increase
  functional coverage and applied it to a Zetta-Hz High Speed CDMA transcei
 ver.\n\nVirtual Program: Presented In-Person
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