BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
DTEND;TZID=America/Los_Angeles:20211206T180000
UID:dac_DAC 2021_sess249_DESPOST116@linklings.com
SUMMARY:Accelerating advanced node ramp up and robust Design Enablement fo
 r leading edge SoC designers
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nAccelerating advanced node ramp up and robust Design Enablement f
 or leading edge SoC designers\n\nKwan\n\nDeveloping advanced technology no
 des entails challenging process ramp up and robust design enablement.   A 
 key deterrent for yield ramp-up and EDA design enablement is the lack of q
 uality and comprehensive layout that effectively probe process capabilitie
 s and design/process interaction.   Process engineers require comprehensiv
 e test cases to evaluate process quality, printability and performance.  D
 esign Enablement teams require layout to calibrate, develop and QA PDKs th
 at enable SoC engineers to design and validate IC.  Guided synthetic layou
 t generation closes the time to resolving these issues.  It generates requ
 isite layouts for test-chip development, silicon measurement, process deve
 lopment, PDK development and Design Enablement.   It provides comprehensiv
 e pattern coverage and stress pattern coverage of the vast design space en
 abling early problem detection and corrective action to productize robust 
 technology nodes and design enablement flows for SoC designers.\n\nSynthet
 ic layout generation used in advanced testchip development accelerates pro
 cess ramp up and design enablement.   We generate test cases to provide br
 oad coverage of the layout pattern space and directed pattern styles to st
 udy stress conditions.  Layouts are placed onto test chips for optical and
  electrical testing.  Testchip silicon measurements drive process node mat
 uration.  Additional layouts accelerate DRC runset, fill and other PDK dev
 elopment for Design Enablement.\n\nVirtual Program: Presented In-Person
END:VEVENT
END:VCALENDAR