BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
DTEND;TZID=America/Los_Angeles:20211206T180000
UID:dac_DAC 2021_sess249_DESPOST119@linklings.com
SUMMARY:Verification Methodology for High Resolution High Speed CMOS Image
  Sensor SoC - Leveraging Innovations in EDA Tools
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nVerification Methodology for High Resolution High Speed CMOS Imag
 e Sensor SoC - Leveraging Innovations in EDA Tools\n\nVishwakarma, Agarwal
 \n\nCMOS Image Sensor SoCs for cinematography, broadcast, and virtual real
 ity applications require ultra-high resolution (>8K) and high frame rate (
 >120FPS) needing a column-parallel readout architecture with each column c
 ontaining more than 10 ADCs and SRAM cells. Verification of such SoCs is e
 xtremely challenging due to the sheer size of the extracted post-layout ne
 tlist which presents a bottleneck in terms of simulation run time, especia
 lly across PVT corners. Another major challenge in verification arises due
  to the complex mixed-signal system architecture with significant interdep
 endency between analog and digital blocks necessitating a rigorous full-ch
 ip functional verification. \nWe present a holistic approach to mitigating
  these challenges synergizing designer’s knowledge with recent innovations
  in EDA tools for analog and mixed-signal design and verification to achie
 ve desired Performance, Accuracy, Capacity and Ease-of-Use (PACE).\nTo hig
 hlight the benefits of our holistic verification methodology we present tw
 o case studies. First, we demonstrate a 3X simulation runtime speedup (wit
 h acceptable jitter) using AFS XT as the analog simulator for extracted bl
 ock-level PLL design. Second, we successfully completed full-chip function
 al verification for our CMOS Image Sensor SoC using Symphony as the mixed-
 signal simulator which provided the capacity and flexibility to implement 
 our hierarchical verification methodology.\n\nVirtual Program: Presented I
 n-Person
END:VEVENT
END:VCALENDAR