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BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
DTEND;TZID=America/Los_Angeles:20211206T180000
UID:dac_DAC 2021_sess249_DESPOST120@linklings.com
SUMMARY:RISC-V processor verification methodology with dynamic testbench f
 or asynchronous events
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nRISC-V processor verification methodology with dynamic testbench 
 for asynchronous events\n\nWright, Lapides\n\nFor SoC designers adopting R
 ISC-V, tackling the processor DV tasks presents some new \nchallenges. The
  established SoC flows have some standard assumptions – test benches writt
 en for UVM SystemVerilog flows and known good processor IP from a mainstre
 am supplier. With the availability of open source RISC-V cores and the gro
 wing interest to modify or add custom extensions is increasing the DV task
 s.\nThe basic RISC-V compliance suite is insufficient to achieve the cover
 age requirements for a complete DV test plan, and comparison-based testing
  with predicted results has built-in limitations. The latest work on dynam
 ic test benches allows the processor RTL to be subjected to the full range
  of asynchronous events and debug operations. Interactive dynamic test ben
 ches allow both detection of issues and also efficient investigation for a
  timely resolution. This paper will present the latest results from extens
 ively testing some popular open source cores with an open test bench.\n\nV
 irtual Program: Presented In-Person
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