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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
DTEND;TZID=America/Los_Angeles:20211206T180000
UID:dac_DAC 2021_sess249_DESPOST127@linklings.com
SUMMARY:Accurate and efficient high-performance memory modeling for full-c
 hip power noise analysis
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nAccurate and efficient high-performance memory modeling for full-
 chip power noise analysis\n\nMirza\n\nLong-established methods of analyzin
 g IR drop contribution of power-grid over RAMs utilize RAM models that fal
 l in two categories. (1) Models that provide SPICE level accuracy but requ
 ire impractical amount of resources to characterize and to analyze large d
 esigns. (2) Models that evenly distribute total power/ground current over 
 the RAM, making model generation and analysis much simpler and faster but 
 lack the accuracy needed to perform signoff with high level of confidence.
  Using any of these methods makes it impossible to simultaneously achieve 
 highly accurate results as well as doing it at the scale required for toda
 y’s large semiconductor designs. NVIDIA and ANSYS teamed up to creat
 e a new RAM modeling method that allows designers to perform IR drop analy
 sis with accuracy and efficiency that could not be achieved with tradition
 al methods. This new method of modeling RAMs for IR drop takes advantage o
 f the structured layout in RAMs and uniformity of vectors needed to trigge
 r worst-case IR drop to greatly simplify characterization and analysis whi
 le maintaining SPICE-like accuracy.\n\nVirtual Program: Presented In-Perso
 n
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