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X-LIC-LOCATION:America/Los_Angeles
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DTSTART:19700308T020000
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DTSTART:19701101T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
DTEND;TZID=America/Los_Angeles:20211206T180000
UID:dac_DAC 2021_sess249_DESPOST133@linklings.com
SUMMARY:AMS Verification of HBMPHY: Challenges & Solutions - 12nm Process 
 Node
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nAMS Verification of HBMPHY: Challenges & Solutions - 12nm Process
  Node\n\nNarawade, Mehta\n\nWe will be presenting our work done on creatin
 g AMS verification setup that uses SV-UVM testbench for HBMPHY chip in 12n
 m technology node. The abstractions used in the design, viz., RTL and tran
 sistor level (TL) based on the design scope are discussed. In doing so, th
 e challenges that we faced were two-fold. One was with respect to handling
  the intricacies involved in the integration of TL in a complex verificati
 on setup, such as SystemVerilog interface array elements connecting to TL 
 (SV to Spice connection). Also, this is a multi-supply design operating at
  four different supply voltages, which added to the complexity in terms of
  associating each of the TL blocks with the correct supplies in such a com
 plex setup. The other challenge was the simulation performance (runtime) b
 ottleneck owing to huge number of IO cells with high frequency DLLs config
 ured in TL. We were able to address these challenges and complete AMS veri
 fication of the chip by framing a mixed-signal verification (MSV) methodol
 ogy that is discussed in this paper. The results thus obtained are capture
 d and the runtime benefits are tabulated.\n\nVirtual Program: Presented In
 -Person
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