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DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
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UID:dac_DAC 2021_sess249_DESPOST139@linklings.com
SUMMARY:PI Signoff Methods Used in a 5nm InFO Design
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nPI Signoff Methods Used in a 5nm InFO Design\n\nKim\n\nSuccess in
  today's electronics market place requires highly integrated chips, at the
  same time, advanced process nodes create new challenges for integration, 
 different advanced 3DIC (including 2.5D) package structures are proposed.\
 n     There are many challenges for 3DIC PI analysis: the modeling of more
  than 100k frontbumps, the mutual interference between multiple dies and p
 ackages, etc. Convergence of these complex circuits requires more effectiv
 e and reliable PI simulation methods. In this paper, the following analyse
 s are performed based on RedHawk-SC, for a TSMC InFO design.\n1.Rap
 id PI Analysis Technology for InFO\nPackage and InFO aware chip PI analysi
 s is successfully performed with wrapped model by RedHawk-SC to obtain a a
 ccurate simulation of the whole system rapidly. \n2.Early-vectorless
  PI Analysis flow\nEarly-vectorless PI analysis flow with propagation can 
 be used in early stages, and has higher weakness coverage than VCD flow. H
 ence, this flow helps to reduce the product time to market.\n3.Effi
 cient Method for PI Iteration \nAn efficient method for PI iteration is pr
 oposed. The method can detect all aggressors in a design and their impact,
  and increase the iteration efficicency finally.\n\nVirtual Program: Prese
 nted In-Person
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