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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
DTEND;TZID=America/Los_Angeles:20211206T180000
UID:dac_DAC 2021_sess249_DESPOST173@linklings.com
SUMMARY:Dual Feature Vector Hetero Graph Neural Network (DFV-GNN) based Po
 st-Layout Parasitic Estimation
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nDual Feature Vector Hetero Graph Neural Network (DFV-GNN) based P
 ost-Layout Parasitic Estimation\n\nKim\n\nParasitic and layout depended ef
 fect (LDE) are become more prominent for advanced node circuit. In this pa
 per, we presented a novel graph neural network based post-layout parasitic
  estimation methodology which can accurately predict both routing and indi
 vidual transistor parasitic based on pre layout schematics. The novelty of
  the approach is elaborated in the following:\nGraph based circuit reducti
 on technique is developed to annotate full post layout extraction informat
 ion into schematics level. We demonstrate pre layout annotated schematic e
 stimation vs full extraction layout final delay time delta can be bounded 
 by within ±5%.\nTo maximize the information from schematic level design, t
 hree layers of attention and SAGE based hetero graph neural network is use
 d. Contrast to previously reported graph neural network based parasitic es
 timation, our circuit graph nodes introduce dual  feature vectors to predi
 ct parasitic of transistor and wire at the same time.\nIndividual transist
 or gate, source and drain parasitic are trained and predicted separately. 
 This will help future transfer learning between different technology nodes
 .\nThe hetero GNN based machine learning model is applied in a most advanc
 ed process node and result error distribution are within +-5% for 3Sigma v
 ariations.\n\nVirtual Program: Presented In-Person
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