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DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
DTEND;TZID=America/Los_Angeles:20211206T180000
UID:dac_DAC 2021_sess249_ESS110@linklings.com
SUMMARY:Performance Modeling of Digital Processing Systems
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nPerformance Modeling of Digital Processing Systems\n\nChandra, Sh
 ankar\n\nPerformance modeling of complex and large processing systems cont
 aining multiple processors, shared memories and multiple application threa
 ds remain inadequate. Conventional modeling approach to predict performanc
 e early in architecture phase relies on modeling methodology utilizing lan
 guages like SystemC are complex and yet yield inaccurate performance data.
  \nThis paper proposes tools and methodology for architecture modeling and
  performance analysis by adopting data flow approach. The modeling approac
 h decouples functionalities and timings thereby significantly reducing com
 plexity. Instead of executing functionally correct software, it performs s
 tatistical analysis of software instructions. Besides predicting performan
 ce, the model also provides high confidence hardware and software design c
 onstraints.\n\nVirtual Program: Presented In-Person
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