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DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
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UID:dac_DAC 2021_sess249_ESS112@linklings.com
SUMMARY:SoC Architectural Exploration for AI and ML accelerators with RISC
 -V
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nSoC Architectural Exploration for AI and ML accelerators with RIS
 C-V\n\nHsu\n\nSoC developers and system designers are looking at hardware 
 acceleration options for AI and Machine Learning applications moving from 
 cloud-based algorithms to dedicated hardware. Since the algorithms are alr
 eady configured for multicore support the tradeoffs become focused on the 
 structure of processor arrays and the optimum performance requirements at 
 each node. In addition to the flexibility offered by the open standard ISA
  of RISC-V to configure the core features to match the compute requirement
 , RISC-V offers the options to add custom extensions and instructions that
  allows a greater degree of system optimization. New extensions can be tar
 geted at the application workload or as dedicated communication channels b
 etween the cores, nodes and/or interfaces to the NoC.  \nThis talk covers 
 a methodology to evaluate the hardware options by enabling early system ar
 chitectural exploration using software to uncover the optimum design confi
 gurations.\n\nVirtual Program: Presented In-Person
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