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DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
DTEND;TZID=America/Los_Angeles:20211206T180000
UID:dac_DAC 2021_sess249_IPPOST101@linklings.com
SUMMARY:Multi-core System Verification Using Uvm Portable Stimulus​
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nMulti-core System Verification Using Uvm Portable Stimulus​
 \n\nKumar\n\nThe fast-moving technological innovations have created a huge
  pressure on silicon requirements which translates to more design complexi
 ty and shrinking time to market. To address the need for reduction in veri
 fication cycle for complex multi-core designs, a scalable and portable met
 hod has been proposed that alleviates the bottlenecks created by conventio
 nal C-based stimuli. Especially in a design containing multiple cores havi
 ng a similar set of peripheral and platform IPs connected to them, the pro
 blem worsens in the conventional approach. The method thus proposed provid
 es a Shift Left approach of creating portable stimuli to such complex mult
 i-core designs.\n\nVirtual Program: Presented In-Person
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