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BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
DTEND;TZID=America/Los_Angeles:20211206T180000
UID:dac_DAC 2021_sess249_IPPOST105@linklings.com
SUMMARY:Updating RISC-V microarchitecture in the field through Menta co-ex
 tended cores and Codasip Studio
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nUpdating RISC-V microarchitecture in the field through Menta co-e
 xtended cores and Codasip Studio\n\nBAILI, Prikryl\n\nThis paper describes
  how Menta and Codasip enable customers to extend processors in systems on
  chip (SoC) after they have been manufactured.\nThe RISC-V ISA is modular 
 and allows custom instructions. Codasip Studio can be used to extend a Cod
 asip core using custom instructions with the necessary additional logic im
 plemented in the datapath. The joint solution allows this extra logic to b
 e implemented in the field using an eFPGA co-extended core.\nSpecialized u
 ser interface tools to program the eFPGA matrix and to set up the RISC-V a
 pplication programmable parameters, will be provided within a complete and
  optimized software solution.\n\nVirtual Program: Presented In-Person
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