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DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
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UID:dac_DAC 2021_sess249_des135@linklings.com
SUMMARY:MOVED TO VIRTUAL: The Reality and Opportunities of Semiconductor D
 esign on the Cloud
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nMOVED TO VIRTUAL: The Reality and Opportunities of Semiconductor 
 Design on the Cloud\n\nKim, Ha, Kim, Do, Kim\n\nAdvanced process nodes, co
 mplex technology requirements and high design complexity lead to more comp
 licated design process than before. Also, it mandates the use of high comp
 uting resources to be able to meet short time-to-market requirement. In ov
 erall, the EDA design infrastructure is moving toward more extensive use o
 f "Cloud" is expected in the future to address aforementioned challenges. 
 Cloud is feasible solution but adoption and management is not easy and fas
 t. A lot of time and efforts are needed and a fine-tuned cloud configurati
 on that considers the characteristics of EDA workloads is required for eff
 icient use of the cloud. Samsung Foundry collaborates with CSP(Cloud Servi
 ce Provider) and EDA partners to provide cloud usage experiences and prope
 r cloud configurations for chip design to help reducing user trial and err
 or through new virtual design environment named SAFE-CDP.(Cloud Design Pla
 tform) \nIn this presentation, I suggest configurations for effectively us
 ing the cloud in EDA workloads and share our experiences of cloud usage in
  SAFE CDP.\n\nVirtual Program: Presented In-Person
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