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DTSTART:19700308T020000
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DTSTART:19701101T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
DTEND;TZID=America/Los_Angeles:20211206T180000
UID:dac_DAC 2021_sess249_des167@linklings.com
SUMMARY:Methodology for early timing and floorplanning closure in custom c
 ircuit design
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nMethodology for early timing and floorplanning closure in custom 
 circuit design\n\nRamamurthy\n\nA pre-layout methodology is disclosed that
  allows designers to achieve a high degree of timing and floorplanning clo
 sure during the early stages of custom macro circuit design.  The methodol
 ogy utilizes Electronic Design Automation (EDA) tools that facilitate an e
 fficient, iterative process of floorplanning a macro using Placement by In
 stance Parameter (PIP) and generating an accurate Steiner estimated parasi
 tic (STEP) RC netlist.  This parasitic netlist is used to provide an early
  and accurate indication of macro performance and timing margins.  Case st
 udies reveal pre- and post-layout timing as well as macro dimension to fal
 l typically within 10%, thus giving high confidence of timing and floorpla
 nning closure early in the design cycle.\n\nVirtual Program: Presented In-
 Person
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