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BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211206T170000
DTEND;TZID=America/Los_Angeles:20211206T180000
UID:dac_DAC 2021_sess249_des201@linklings.com
SUMMARY:MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug
  for High Performance Microprocessor Designs
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nMOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debu
 g for High Performance Microprocessor Designs\n\nJoseph, Rachamalla, Ghosh
 , Reddy, Joy...\n\nIn the microprocessor design cycle, time spent in the h
 ardware lab is crucial. There is a need to resolve issues seen in the hard
 ware lab as quickly as possible. The data available from hardware is parti
 al. Access to more expanded data based on this partial hardware dump data 
 helps lab debug significantly. Design flows using a step-wise refinement i
 mplementation present new opportunities to perform hardware debug in the s
 implified design intent (NMZ) model of hardware. We introduce LabReplay, t
 he first such post-silicon debug flow, to create “expanded” ha
 rdware debug data set in the “simpler” NMZ model. Compared to 
 current state of art techniques, LabReplay uniquely brings together 3 key 
 aspects: 1) "Shift right” the principle of Designer Level Verificati
 on 2) Perform “replay” on the simpler NMZ model of hardware 3)
  And the new application of X-state simulation. Experimental evaluation of
  LabReplay on industry-class next-generation high-performance microprocess
 or designs, like the IBM POWER10, demonstrate the efficiency of the approa
 ch. We believe the techniques described are generic and advocate the appli
 cation of these techniques to complement existing post-silicon hardware la
 b debug.\n\nVirtual Program: Presented In-Person
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