BEGIN:VCALENDAR VERSION:2.0 PRODID:Linklings LLC BEGIN:VTIMEZONE TZID:America/Los_Angeles X-LIC-LOCATION:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:19700308T020000 RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:19701101T020000 RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20211208T164510Z LOCATION:Level 2 - Exhibit Hall DTSTART;TZID=America/Los_Angeles:20211208T170000 DTEND;TZID=America/Los_Angeles:20211208T180000 UID:dac_DAC 2021_sess251@linklings.com SUMMARY:Designer, IP and Embedded Systems Track Poster Networking Receptio n DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece ption\n\nEfficient High-Sigma Verification of Standard Cell Libraries\n\nE vans, Namekumar\n\nGiven the increasing complexity and variability of stat e-of-the-art process technologies, circuit functionality must be robust to ensure high chip yields. Arm Physical Design Group develops standard cell library products across various foundries and process technologies. Flip- flop cells within these...\n\n---------------------\nRobust Timing Analysi s And Optimization under Parametric On-Chip Process Variation\n\nChai\n\nD esign considering variation is required in order to maximize profit and im prove PPA because variation impact is increased in the deep-sub micron tec hnilogies The existing POCV method to deal with variation doesn't conside r block level timing impact while it applies variation impact on each path . I...\n\n---------------------\nOptimizing hold eco using ML techniques\n \nAgrawal, Deshmukh, Yogi\n\nConventional ECO tools fix hold violations pr imarily by using cell delays through hold-buffer additions, cell downsizin g, Vt swaps. Significant addition of delay cells can lead to congestion. F urther cell delays do not scale uniformly across corners and can lead to s etup-hold critical paths.\n\nThis p...\n\n---------------------\nCANCELLED : Rethinking New Product Introduction to Better Align to Client Needs\n\nH ackathorn\n\nEven with decades of product development experience, the team continuously revises the new product introduction (NPI) process to maximi ze product innovation and alignment to client needs. \n\nRapidly increasin g computing power and connectivity for Internet of Things (IoT) devices dr ove significant new...\n\n---------------------\nECO patch generation & st itching to facilitate concurrent ECOs in High Performance Processor Design s\n\nEarl\n\nAs design sizes increase, the number of last minute changes(E CO) and the time required to process them(TAT) also increase. During the f ag end of the design cycle owing to the congestion a small change can lead to massive impact in terms of timing & routing resources & can greatly ha mper chip schedul...\n\n---------------------\nAttaining Consistent RTL Qu ality and Improving Development Cycles with GIT Continuous Integration Too ls\n\nHupcey\n\nIntroduction: Developments are consistently under schedule pressure with limited resources, leaving little room for surprises in dev elopment. \n\nCurrent challenge: ASIC and FPGA developments become unpred ictable due to challenges in functional verification. This uncertainty of ten results from lesse...\n\n---------------------\nRoot-cause analysis of undefined slack using timing/netlist data model\n\n.\n\nUndefined or not- computed (NC) slack can happen in a design for multiple reasons, for insta nce dis-connected wires, dis-connected gates, phase-pair excluded tests a mongst others. A design has to be NC clean to get a passing grade. Debuggi ng the root-cause of NC slack is however a tedious and time-c...\n\n------ ---------------\nA Low Cost, Scalable and Predictable Gate Level Simulatio n Methodology for Giga-Scale SOCs\n\nNaicker\n\nIncreasing time-to-market pressure with short convergence cycle runway for giga-scale SOCs mandates a GLS methodology that’s cost effective, scalable and predictable. G LS on giga-scale SOCs is costly due to below reasons :-\na. High initial bring-up cost for infrastructure and testbench.\nb. P...\n\n------------- --------\nHybrid Emulation Methodology for SSD Design\n\nLee\n\nAs SSD des ign gets more complicated, faster simulation for HW/FW co-verification is heavily required to improve time-to-market. Hybrid emulation is a viable s olution to achieve the requirement by combining a virtual platform with an emulator. In this work, we propose a hybrid emulation methodology c...\n\ n---------------------\nMachine learning Assisted Design Rule Debug and Ru le Ranking Automation\n\nFu\n\nDesign Technology Co-optimization (DTCO) is the key driver for advanced node process development. Design rules change request design exploration are evaluated by the process development litho graphy team. This paper developed a Machine learning assisted design rule debug system to help technologist a...\n\n---------------------\nA flexibl e SAR-ADC IP for multiple technodes\n\nReich, Prautsch, Jotschke\n\nWe pre sent an novel charge-redistribution SAR-ADC, which is featured by covering sampling rates from 100 Sps up to 2 MSps with high accuracy up to 11 bit ENOB.\nWe achieve Ultra-low-power consumption down to 2.3 µW @ 10kSps for IoT and medical applications. The SAR-ADC IP is silicon-proven in various. ..\n\n---------------------\nPioneering Low Power Modeling and Verificatio n Technique for custom blocks\n\nSrinivasan\n\nFPGA designs contain differ ent kind of blocks. The Unified Power Intent (UPF) flow is streamlined for an ASIC block. However, power intent verification is not fully streamline d for pure custom and analog blocks. Custom blocks present challenges in n etlisting flow, UPF coding, error counts in static ...\n\n---------------- -----\nMulti-Physics Simulation Techniques toward Electromagnetic Side-Cha nnel Attack Assessments on IC Chip Assembly\n\nLin\n\nElectromagnetic (EM) emission from IC chips carries secret information of cryptographic proces sing because EM side channel leakage directly related with power current c onsumption during the operation of crypto ICs. Simulation-based EM side-ch annel analysis provides flexible design-time optimization ...\n\n--------- ------------\nPredicting Timing Bottlenecks in Place & Route using Machine Learning\n\nBelhadj\n\nSystem-on-Chip (SoC) design implementation is comp lex and challenging. The outcome is influenced by lots of variables, rangi ng from circuit design to process technology. It is a costly and time-cons uming process for experienced designers to iterate over multiple floorplan s before arriving at one tha...\n\n---------------------\nExpediting Data Converter Layouts using Design Planning & Analysis (DPA) Automation\n\nTho mpson, Kumar, Bhargava, LaBorde\n\nHierarchical Designs are challenging to plan and estimate while layout implementation specially when sub-cells la yout views are not present throughout the hierarchy. Generate All From Sou rce for top cell generates all hierarchical contents flat at top layout vi ew, this becomes very challenging to fl...\n\n---------------------\nShift -left Post-Silicon verification with Speed and Accuracy\n\nMonroy\n\nIn ea rly days, Post-silicon validation was crucial before market release to che ck the accuracy of any chip and due to early-to-market need, techniques to use such methods got easier using simulators support at very initial stag es e.g. alpha, beta, early, limited and release of RTL. Simulator support. ..\n\n---------------------\nA Spring Model Approach For Timing Budget App ortionment\n\nKo\n\nIn a hierarchical design, timing budget would need to be split up properly between macros and levels of hierarchy so that the sy nthesis effort can be carried out efficiently. It is essential to have a robust method to determine the AT/RAT assertions for macro inputs/outputs so that the optimization...\n\n---------------------\nCANCELLED: Fast Trac king a Federal Authentication Solution for Secure Facilities\n\nGarcia\n\n A federal security agency urgently needed an edge computing solution that helped them verify an individual's identity before allowing them to enter secure facilities. The end solution needed to run the agency’s exist ing authorization software while also collecting user authentication data via ...\n\n---------------------\nAlgorithm to RTL: A Faster Path to Imple mentation\n\nKlein, Saha\n\nWhen designing hardware, logic designers often need to implement an algorithm where a reference implementation exists as a software function. High-level Synthesis (HLS) is an approach that conv erts an algorithm’s C/C++ implementation to a synthesizable hardware descr iption. However, to get a good ...\n\n---------------------\nCANCELLED: S tress Testing to Survive an Industrial Gas Turbine\n\nMcNamara\n\nA client that designs and manufactures industrial gas turbines for onshore and off shore electrical power generation, marine propulsion, and for producing/pr ocessing/transporting natural gas and oil needed a new computerized monito ring system. \n\nWhile the architecture of a ruggedized edge computing .. .\n\n---------------------\nEnhanced Analytics and Reporting for Triage an d Sign-off Timing\n\nKalafala, Taggart\n\nDeveloping insights for problems produced by Static Timing Analysis (STA) and optimization for high perfor mance microprocessor designs requires in-depth analysis of both timing and physical data; this is a big data problem. This task has four main challe nges, including: managing design hierarchy, re...\n\n--------------------- \nCANCELLED: Modernizing Public Infrastructure with Interactive Devices\n\ nGray\n\nA large American city sought to convert over 7,000 payphones acro ss the city into a public, citywide Wi-Fi network. The goal was to create free, encrypted, gigabit wireless Internet coverage and displays for publi c engagement by converting old payphones into slim-profile edge devices ar ound the city...\n\n---------------------\nClocking Methods with Focus on PCIe Gen4\n\nFong\n\nGood clock latency and skew can be hard to attain on complex IP when using default settings. Difficulties during clock build wi th PCIe Gen4 with a certain vendor has been strenuous and time-consuming. In this design, the clock and design are overly complex with multiple IP c onfigurations and over 36...\n\n---------------------\nUsing Clock Skew to Fix Hold: A Path-Depth Based Useful-Skew Approach to Reduce Hold Buffer I nsertion\n\nGerstner\n\nModern clock tree synthesis (CTS) algorithms take advantage of useful skew to improve setup time performance by increasing t he insertion delay to the capture flop on a setup-critical path. This impr oves setup total-negative slack at the cost of additional buffering on the clock network. However, the...\n\n---------------------\nPriority Synthes is in Physical Synthesis\n\nReddy\n\nPhysical Synthesis uses estimated rel ative timing criticality to prioritize critical regions during design timi ng closure. This also applies to dispensing limited precious resources ava ilable such as lower-vt, wider wires. However, it is possible that more-cr itical regions may be closed easily by lo...\n\n---------------------\nFas t and Accurate DvD aware Timing Analysis\n\nSwinnen\n\nOn-chip resistance and cell density are getting increase, especially 7nm technology and below which causes local voltage drop hot-spots that would be occurred dynamica lly depending on the analysis scenario. Analyzing the impact of dynamic be havior of voltage drop on timing of critical path is requir...\n\n-------- -------------\nEnhanced Hyperscaling of Data Centers using In-Chip Monitor ing & Sensing Fabrics\n\nMassoudi\n\nThe development of High Performance C omputing (HPC) chips on a large scale for datacentre platforms poses many challenges associated with multi-processor architectures working on high c omputational workloads. This presentation explores the interplay between t hermal management, power distribution, pr...\n\n\nVirtual Program: Present ed In-Person END:VEVENT END:VCALENDAR