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DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Exhibit Hall
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UID:dac_DAC 2021_sess251_DESPOST126@linklings.com
SUMMARY:Optimizing hold eco using ML techniques
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nOptimizing hold eco using ML techniques\n\nAgrawal, Deshmukh, Yog
 i\n\nConventional ECO tools fix hold violations primarily by using cell de
 lays through hold-buffer additions, cell downsizing, Vt swaps. Significant
  addition of delay cells can lead to congestion. Further cell delays do no
 t scale uniformly across corners and can lead to setup-hold critical paths
 .\n\nThis paper explores an alternate approach for hold-buffer addition, w
 herein a delay for hold fix is translated to a combination of cell-delay, 
 net-delay, transition, and capacitance values. Window-based filters for me
 asuring congestion are generated around the endpoint wherein the intended 
 buffers will be placed. Our work is based on ML-based real-time filtering 
 of physical data to create a run-set holding the available hold-buffers, f
 anout, metal-layers, transition, capacitance values, across multiple-corne
 rs. Considering non-linearity of the physical aware parameters - SVM, KNN,
  and Decision Tree classifiers are a few of the approaches involved to pro
 vide the best optimal eco. In contrast to contemporary solutions for fixin
 g hold violations, this solution is novel in its approach by involving rea
 l-time data for optimizing the required set of physical components by usin
 g supervised learning approaches.\nOur approach is well scalable and well 
 suited to multiple technology nodes and can be utilized at any level of ar
 chitectural framework in the physical design domain.\n\nVirtual Program: P
 resented In-Person
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