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DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211208T170000
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UID:dac_DAC 2021_sess251_DESPOST129@linklings.com
SUMMARY:Predicting Timing Bottlenecks in Place & Route using Machine Learn
 ing
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nPredicting Timing Bottlenecks in Place & Route using Machine Lear
 ning\n\nBelhadj\n\nSystem-on-Chip (SoC) design implementation is complex a
 nd challenging. The outcome is influenced by lots of variables, ranging fr
 om circuit design to process technology. It is a costly and time-consuming
  process for experienced designers to iterate over multiple floorplans bef
 ore arriving at one that meets the performance, power and area (PPA) targe
 ts. By shortening the time used for floorplan exploration, chip makers can
  improve Time-To-Market and reduce development cost.\n\nThis collaboration
  between Infineon Technologies and Plunify utilizes Machine Learning to pr
 edict the timing bottlenecks in any given floorplan. We leverage domain kn
 owledge and past design data to train a Deep Learning model. Once trained,
  the model predicts timing bottlenecks in a heatmap format for any input f
 loorplan, allowing designers to make a Go/No-go decision within seconds. I
 f a floorplan is deemed unsuitable, designers can re-work it to resolve th
 e bottlenecks as predicted by the model.\n\nVirtual Program: Presented In-
 Person
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