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DTSTART:19700308T020000
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DTSTART:19701101T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211208T170000
DTEND;TZID=America/Los_Angeles:20211208T180000
UID:dac_DAC 2021_sess251_DESPOST131@linklings.com
SUMMARY:Robust Timing Analysis And Optimization under Parametric On-Chip P
 rocess Variation
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nRobust Timing Analysis And Optimization under Parametric On-Chip 
 Process Variation\n\nChai\n\nDesign considering variation is required in o
 rder to maximize profit and improve PPA because variation impact is increa
 sed in the deep-sub micron technilogies  The existing POCV method to deal 
 with variation doesn't consider block level timing impact while it applies
  variation impact on each path. In this study, we propose a methid to anal
 yze and optimize the timing impact due to variation at the block level.\n\
 nVirtual Program: Presented In-Person
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