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DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211208T170000
DTEND;TZID=America/Los_Angeles:20211208T180000
UID:dac_DAC 2021_sess251_DESPOST132@linklings.com
SUMMARY:A Low Cost, Scalable and Predictable Gate Level Simulation Methodo
 logy for Giga-Scale SOCs
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nA Low Cost, Scalable and Predictable Gate Level Simulation Method
 ology for Giga-Scale SOCs\n\nNaicker\n\nIncreasing time-to-market pressure
  with short convergence cycle runway for giga-scale SOCs mandates a GLS me
 thodology that’s cost effective, scalable and predictable. GLS on gi
 ga-scale SOCs is costly due to below reasons :-\na. High initial bring-up
  cost for infrastructure and testbench.\nb. Predictability issues with hu
 ge monolithic models having capacity and runtime issues.\nc.  Models with
  no modular debug hooks.\nThe ‘Hybrid GLS’ approach with 'Shad
 ow RTL' methodology presented in here addresses these concerns and the res
 ults obtained as well as the gains of the approach are shared - as reporte
 d from two generations of giga-scale SOC tapeouts. The methodology present
 ed has successfully been applied at IP, Subsystem as well as SOC levels an
 d the qualitative as well as quantitative gains have been presented.\n\nVi
 rtual Program: Presented In-Person
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