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BEGIN:VEVENT
DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211208T170000
DTEND;TZID=America/Los_Angeles:20211208T180000
UID:dac_DAC 2021_sess251_DESPOST148@linklings.com
SUMMARY:Root-cause analysis of undefined slack using timing/netlist data m
 odel
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nRoot-cause analysis of undefined slack using timing/netlist data 
 model\n\n.\n\nUndefined or not-computed (NC) slack can happen in a design 
 for multiple reasons, for instance dis-connected wires, dis-connected gate
 s,  phase-pair excluded tests amongst others. A design has to be NC clean 
 to get a passing grade. Debugging the root-cause of NC slack is however a 
 tedious and time-consuming activity for designers. \nTiming analysis tool 
 generates a timing NC-report that lists test points where it has NC slack.
  The problem is that the root-cause of NC slack many a times can be due to
  an issue upstream of a path and not at the pin reported in the timing rep
 ort. The root-cause coverage of a timing report can vary wildly---from 68%
  to 78% in our benchmarking---based on a design.  \nIn this work we have d
 eveloped a netlist design data based solution in Python that looks for tho
 se pins that timing NC-report couldn't root-cause and show that the covera
 ge now is well over 97% (and increasing), thus providing significant produ
 ctivity improvements to designers. The script is deployed and is being use
 d actively by designers.\n\nVirtual Program: Presented In-Person
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