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DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211208T170000
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UID:dac_DAC 2021_sess251_DESPOST163@linklings.com
SUMMARY:Enhanced Analytics and Reporting for Triage and Sign-off Timing
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nEnhanced Analytics and Reporting for Triage and Sign-off Timing\n
 \nKalafala, Taggart\n\nDeveloping insights for problems produced by Static
  Timing Analysis (STA) and optimization for high performance microprocesso
 r designs requires in-depth analysis of both timing and physical data; thi
 s is a big data problem. This task has four main challenges, including: ma
 naging design hierarchy, reporting, linking data across time, and providin
 g a reliable and scalable platform. Our new system extends the Design Data
  (DD) model using a hybrid data store architecture and methodology. This s
 ystem addresses the above challenges for circuit design analysis and debug
 .\n\nThe DD model efficiently stores read-only netlist, timing, power, and
  physical (e.g., placement, congestion, routing) data in a compressed bina
 ry file on disk. Furthermore, DD contains the full timing graph enabling e
 fficient path traversal and custom interactive analysis. This binary file 
 is extended with a timing path-based “hybrid cache data store” using an SQ
 L database and custom DD WebSocket server.\n\nDesigners can generate metri
 cs charts to evaluate progress and focus efforts over a project’s life cyc
 le. They can compare past and current data sets to identify and assess spe
 cific design trends and failure modes. Designers can define custom rules t
 o categorize, filter, triage, and assign timing paths which need to be fix
 ed, even across multi-year projects.\n\nVirtual Program: Presented In-Pers
 on
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