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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211208T170000
DTEND;TZID=America/Los_Angeles:20211208T180000
UID:dac_DAC 2021_sess251_DESPOST170@linklings.com
SUMMARY:Pioneering Low Power Modeling and Verification Technique for custo
 m blocks
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nPioneering Low Power Modeling and Verification Technique for cust
 om blocks\n\nSrinivasan\n\nFPGA designs contain different kind of blocks. 
 The Unified Power Intent (UPF) flow is streamlined for an ASIC block. Howe
 ver, power intent verification is not fully streamlined for pure custom an
 d analog blocks. Custom blocks present challenges in netlisting flow, UPF 
 coding, error counts in static checks and liberty modeling for the power r
 elated cells. For custom blocks, transistors need to be properly modeled i
 n the netlist. UPF needs to be simplified and coded correctly. Power cells
  needs to be modeled correctly using liberty models. Results needs to be i
 n a reasonable number for easy review. Hence, proper violation tags need t
 o be chosen in a static verification tool. Custom blocks UPF flow needs to
  be modeled correctly, simple to use, scalable, easy to review. This will 
 ensure that both ASIC and custom blocks can UPF standard with low power to
 ols for their power intent definition and verification. Through this paper
 , a novel innovative approach for verifying custom blocks is presented.\n\
 nVirtual Program: Presented In-Person
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