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DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211208T170000
DTEND;TZID=America/Los_Angeles:20211208T180000
UID:dac_DAC 2021_sess251_DESPOST175@linklings.com
SUMMARY:Algorithm to RTL: A Faster Path to Implementation
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nAlgorithm to RTL: A Faster Path to Implementation\n\nKlein, Saha\
 n\nWhen designing hardware, logic designers often need to implement an alg
 orithm where a reference implementation exists as a software function.  Hi
 gh-level Synthesis (HLS) is an approach that converts an algorithm’s C/C++
  implementation to a synthesizable hardware description.  However, to get 
 a good hardware implementation the developer needs to introduce parallelis
 m and concurrency to the algorithm, while considering the area impacts of 
 each modification.  This requires a deep understanding of the algorithm an
 d of the transformations that the HLS compiler performs while generating t
 he hardware implementation from the input code.  This can be daunting for 
 even expert designers.  Gaining an understanding of the data dependencies 
 and opportunities for parallelism in a software implementation by “staring
  at the code” is inefficient and impractical. Furthermore, going through a
 n iterative synthesis and performance evaluation flow is extremely time co
 nsuming. We introduce an approach that analyzes the input algorithm to det
 ermine the characteristics needed for a good HLS implementation. This data
  is used to create  configuration files and code annotations to steer the 
 HLS compiler, without the developer needing an intimate understanding of t
 he reference implementation.  An evaluation with a set of representative k
 ernels showed gains between 5-600x, when compared with a sequential HW imp
 lementation.\n\nVirtual Program: Presented In-Person
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