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BEGIN:VEVENT
DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211208T170000
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UID:dac_DAC 2021_sess251_DESPOST176@linklings.com
SUMMARY:Attaining Consistent RTL Quality and Improving Development Cycles 
 with GIT Continuous Integration Tools
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nAttaining Consistent RTL Quality and Improving Development Cycles
  with GIT Continuous Integration Tools\n\nHupcey\n\nIntroduction: Developm
 ents are consistently under schedule pressure with limited resources, leav
 ing little room for surprises in development. \n\nCurrent challenge:  ASIC
  and FPGA developments become unpredictable due to challenges in functiona
 l verification.  This uncertainty often results from lesser quality RTL co
 de.  Challenging debug and hard-to-find issues are caused by common mistak
 es in design and coding.   While static and formal verification tools find
  these issues, problems ensue without consistent use and enforcement.  \n\
 nProposed solution: Integrating static and formal verification tools into 
 both the check-in and regression processes can augment functional verifica
 tion, resulting in less uncertainty.  The more integrated with the code re
 positories, the easier it should be to implement and enforce.  \n\nOur pro
 posed solution integrates these tools into our automated GIT Continuous In
 tegration flow, an example being the open-source GITLAB-CI.   By implement
 ing quality checks of increasing rigor to check-ins, nightly regressions, 
 and weekly regressions, across integrated testing domains such as SystemVe
 rilog random stimulus testing, code-coverage checking, static Lint, formal
  Lint and clock/reset domain crossing checks, we should see more predictab
 le, efficient development. \n\nResults:  We observed the expected results 
 with a minimum of effort due to the ease of using GITLAB-CI.  Results will
  be available upon acceptance.\n\nVirtual Program: Presented In-Person
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