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DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211208T170000
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UID:dac_DAC 2021_sess251_DESPOST183@linklings.com
SUMMARY:Efficient High-Sigma Verification of Standard Cell Libraries
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nEfficient High-Sigma Verification of Standard Cell Libraries\n\nE
 vans, Namekumar\n\nGiven the increasing complexity and variability of stat
 e-of-the-art process technologies, circuit functionality must be robust to
  ensure high chip yields. Arm Physical Design Group develops standard cell
  library products across various foundries and process technologies. Flip-
 flop cells within these libraries must have their functionality verified t
 o ensure that internal failure mechanisms will not cause yield loss. Compu
 te and turnaround time costs are too expensive when using brute force mont
 e-carlo simulation to perform this verification at high-sigma functional y
 ield. Siemens EDA has developed the Worst-Case Yield Solver (WCYS) flow as
  part of the Solido Variation Designer tool enabling Arm to verify flop fu
 nctionality to 6-sigma yields and beyond. To further reduce compute and tu
 rnaround time costs, Arm runs the WCYS flow in the cloud. Arm and Siemens 
 EDA are working to enable the WCYS flow on Arm architecture machines in th
 e cloud to realize further compute cost savings compared to alternate CPU 
 architectures.\n\nVirtual Program: Presented In-Person
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