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BEGIN:VEVENT
DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211208T170000
DTEND;TZID=America/Los_Angeles:20211208T180000
UID:dac_DAC 2021_sess251_IPPOST103@linklings.com
SUMMARY:Shift-left Post-Silicon verification with Speed and Accuracy
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nShift-left Post-Silicon verification with Speed and Accuracy\n\nM
 onroy\n\nIn early days, Post-silicon validation was crucial before market 
 release to check the accuracy of any chip and due to early-to-market need,
  techniques to use such methods got easier using simulators support at ver
 y initial stages e.g. alpha, beta, early, limited and release of RTL. Simu
 lator support is really helpful to narrow down almost all the bugs in logi
 c path at very early stage of verification. But on the other hand, some of
  the realtime validation techniques are least viable on simulators for e.g
 . Fault/Defect Testing, Functional/Stress validation, hardware/software co
 -validation and performance validation. One of the examples under the cate
 gory of Fault/Defect testing, DFT verification techniques are widely recog
 nised to unfold design bugs and perform efficient functional verification.
  But over the past years, design got bigger in size and complex in logic d
 ensity, which also resulted to increase complexity in test-glue around DUT
 . Hardware acceleration support on such verification techniques make it fa
 irly easy and faster to do DFT closure with a reduction of months efforts 
 to days. Prototyped version of your RTL running on a mega-hertz speed make
 s it faster and easier enough to re-iterate the whole process of DFT verif
 ication.\n\nVirtual Program: Presented In-Person
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