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BEGIN:VEVENT
DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211208T170000
DTEND;TZID=America/Los_Angeles:20211208T180000
UID:dac_DAC 2021_sess251_des169@linklings.com
SUMMARY:Using Clock Skew to Fix Hold: A Path-Depth Based Useful-Skew Appro
 ach to Reduce Hold Buffer Insertion
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nUsing Clock Skew to Fix Hold: A Path-Depth Based Useful-Skew Appr
 oach to Reduce Hold Buffer Insertion\n\nGerstner\n\nModern clock tree synt
 hesis (CTS) algorithms take advantage of useful skew to improve setup time
  performance by increasing the insertion delay to the capture flop on a se
 tup-critical path. This improves setup total-negative slack at the cost of
  additional buffering on the clock network. However, these useful skew CTS
  engines do not simultaneously skew to minimize hold negative slack; hold 
 is fixed in the conventional manner of adding delay buffers at the last st
 age of the design flow, when area for these buffers is scarce. This presen
 tation will illustrate a novel approach whereby an exhaustive path depth a
 nalysis is performed on a post-routed netlist to identify launching flops 
 with little functional (non-buffer) logic on their transitive fanout, but 
 with a large number of hold buffers in this same fanout. Based on the post
 -signoff clock arrival times at these launch/capture flops, positive skew 
 adjustments are computed for the target launching flops. By re-running the
  CTS and routing portions of the backend flow with these increased latency
  targets on hold-critical flops, the hold buffer count can be reduced. Usi
 ng a commercial physical implementation flow, IP processor core, and cell 
 library, results show a reduction in hold buffer count of up to 35%.\n\nVi
 rtual Program: Presented In-Person
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