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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211208T170000
DTEND;TZID=America/Los_Angeles:20211208T180000
UID:dac_DAC 2021_sess251_des208@linklings.com
SUMMARY:ECO patch generation & stitching to facilitate concurrent ECOs in 
 High Performance Processor Designs
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nECO patch generation & stitching to facilitate concurrent ECOs in
  High Performance Processor Designs\n\nEarl\n\nAs design sizes increase, t
 he number of last minute changes(ECO) and the time required to process the
 m(TAT) also increase. During the fag end of the design cycle owing to the 
 congestion a small change can lead to massive impact in terms of timing & 
 routing resources & can greatly hamper chip schedules. So, when multiple l
 ast minute changes arrive it is necessary to categorize must haves, good t
 o haves & determine the implementable ones & apply the ECO change. As mult
 iple ECOs arrive over a period it becomes TAT inefficient to apply ECOs se
 quentially for evaluation & ECO application. So, there is a need for a met
 hodology to facilitate concurrent processing of individual ECOs to determi
 ne ECO acceptability & an ability to merge accepted ECO changes. This pres
 entation describes a tool (mdiff) and a methodology (ECO stitching) to all
 ow unrelated ECOs on a design to be implemented in parallel on copies of t
 he design and then applied to single copy for reduced TAT.\n\nVirtual Prog
 ram: Presented In-Person
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