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BEGIN:VEVENT
DTSTAMP:20211208T164412Z
LOCATION:Level 2 - Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20211208T170000
DTEND;TZID=America/Los_Angeles:20211208T180000
UID:dac_DAC 2021_sess251_des254@linklings.com
SUMMARY:Clocking Methods with Focus on PCIe Gen4
DESCRIPTION:Designer, IP and Embedded Systems Track Poster Networking Rece
 ption\n\nClocking Methods with Focus on PCIe Gen4\n\nFong\n\nGood clock la
 tency and skew can be hard to attain on complex IP when using default sett
 ings. Difficulties during clock build with PCIe Gen4 with a certain vendor
  has been strenuous and time-consuming. In this design, the clock and desi
 gn are overly complex with multiple IP configurations and over 36 clocks. 
 The four methods developed are regioning PCIe logic, analyzing the skew gr
 oups, inserting a h-tree, and refraining certain clocks to be balanced. Th
 e methods improved turnaround time, clock skew, and clock latency; therefo
 re, attaining an acceptable clock tree in a reasonable time frame and enab
 ling successful tapeouts on multiple projects.\n\nVirtual Program: Present
 ed In-Person
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