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VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
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TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
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BEGIN:VEVENT
DTSTAMP:20211208T164405Z
LOCATION:DAC Pavilion
DTSTART;TZID=America/Los_Angeles:20211206T140000
DTEND;TZID=America/Los_Angeles:20211206T144500
UID:dac_DAC 2021_sess259_PAV107@linklings.com
SUMMARY:Trust and verify.  Overcoming costly and piecemeal approaches to p
 re-silicon side-channel attack vulnerability analysis and verification
DESCRIPTION:DAC Pavilion Panels\n\nTrust and verify.  Overcoming costly an
 d piecemeal approaches to pre-silicon side-channel attack vulnerability an
 alysis and verification\n\nSanto, Santo, Ruby, Borza, Mishra\n\nSide-chann
 el vulnerabilities strike fear into the hearts of design engineers – as we
 ll as corporate lawyers and executives. But analyzing and uncovering poten
 tial vulnerabilities can be costly and time-consuming. Existing EDA tool f
 lows aren’t adequate to meet the challenges, so analysis is typically perf
 ormed after the first-silicon prototype tapeout. This requires expertise a
 nd can prompt expensive silicon re-spins. The clear and present danger of 
 side channel attacks, and the lack of a robust EDA security analysis metho
 dology are creating a critical need for dedicated physical attack simulati
 on tools that can root out vulnerabilities before prototype. \n\nPanelists
  will discuss the gaps and downsides of current and new tools as well as a
  path forward to timely, efficient, and thorough pre-silicon side-channel 
 attack vulnerability analysis. How can you better secure your design witho
 ut hampering your design schedule and cost? Bring your questions – it shou
 ld be a lively discussion!\n\nVirtual Program: Presented In-Person
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