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DTSTAMP:20211208T164509Z
LOCATION:DAC Pavilion
DTSTART;TZID=America/Los_Angeles:20211206T163000
DTEND;TZID=America/Los_Angeles:20211206T173000
UID:dac_DAC 2021_sess260@linklings.com
SUMMARY:Designer, IP, and Embedded Systems Poster Gladiators Presentation
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nThe D
 esigner, IP and Embedded Tracks Poster presentations will be eligible to w
 in the prestigious DAC Gladiator Poster Award.  These selected posters wil
 l present their posters live on Monday-Wednesday from 4 -5 PM in the DAC  
 Pavilion. Winners of the award will be announced and recognized on Wednesd
 ay.\n\nRoutability Improvement Methodology Using Multiple Standard Cells w
 ith Various Pin Location\n\nKwon, Kim, Park, Shin, Shin...\n\nWe introduce
  a new design method for routability improvement . It can contributes to s
 ave routing resource by using direct pin connection with multiple standard
  cells with various pin location in advanced node suffered by low layer PD
 N and more dense metal usage for pin shape. The proposed direct lo...\n\n-
 --------------------\nEnhanced Analytics and Reporting for Triage and Sign
 -off Timing\n\nKalafala, Taggart\n\nDeveloping insights for problems produ
 ced by Static Timing Analysis (STA) and optimization for high performance 
 microprocessor designs requires in-depth analysis of both timing and physi
 cal data; this is a big data problem. This task has four main challenges, 
 including: managing design hierarchy, re...\n\n---------------------\nA Lo
 w Cost, Scalable and Predictable Gate Level Simulation Methodology for Gig
 a-Scale SOCs\n\nNaicker\n\nIncreasing time-to-market pressure with short c
 onvergence cycle runway for giga-scale SOCs mandates a GLS methodology tha
 t’s cost effective, scalable and predictable. GLS on giga-scale SOCs
  is costly due to below reasons :-\na. High initial bring-up cost for inf
 rastructure and testbench.\nb. P...\n\n---------------------\nA Scalable 
 Multicore RISC-V GPGPU Accelerator for High-End FPGAs\n\nTine, Elsabbagh\n
 \nThe recent generation of high-end FPGAs provide a high computational cap
 ability, and energy-efficient makes them attractive in high-performance co
 mputation and architecture research thanks to their reconfigurability. Exp
 loring the implementation of a high-bandwidth accelerator on these large F
 PGAs p...\n\n---------------------\nAbstraction- An efficient methodology 
 for RTL & Low-Power Signoff in SoC Design\n\nSinha\n\nIn the pursuit of ze
 ro Si bug in with predictable schedules, it is extremely important for RTL
  designers to signoff a good quality RTL to the verification as well as im
 plementation team to ensure that there are minimal ECOs.\nFor hierarchical
  SoC, while QoR stub flow or grey box flow comes with accur...\n\n--------
 -------------\nEnhanced Hyperscaling of Data Centers using In-Chip Monitor
 ing & Sensing Fabrics\n\nMassoudi\n\nThe development of High Performance C
 omputing (HPC) chips on a large scale for datacentre platforms poses many 
 challenges associated with multi-processor architectures working on high c
 omputational workloads. This presentation explores the interplay between t
 hermal management, power distribution, pr...\n\n---------------------\nShi
 ft-left Post-Silicon verification with Speed and Accuracy\n\nMonroy\n\nIn 
 early days, Post-silicon validation was crucial before market release to c
 heck the accuracy of any chip and due to early-to-market need, techniques 
 to use such methods got easier using simulators support at very initial st
 ages e.g. alpha, beta, early, limited and release of RTL. Simulator suppor
 t...\n\n---------------------\nTowards measuring layout pattern coverage: 
 a Machine Learning Approach\n\nFu\n\nDifferent types of layout pattern are
  used for yield learning. Despite finding a representative layout pattern 
 is crucial, there is no formal and reliable method to measure the layout p
 attern coverage. Traditional high dimension reduction techniques such as t
 SNE, SoM (Self organized map) are used to...\n\n\nVirtual Program: Present
 ed In-Person
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