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BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:DAC Pavilion
DTSTART;TZID=America/Los_Angeles:20211206T163000
DTEND;TZID=America/Los_Angeles:20211206T173000
UID:dac_DAC 2021_sess260_DESPOST113@linklings.com
SUMMARY:Abstraction- An efficient methodology for RTL & Low-Power Signoff 
 in SoC Design
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nAbstr
 action- An efficient methodology for RTL & Low-Power Signoff in SoC Design
 \n\nSinha\n\nIn the pursuit of zero Si bug in with predictable schedules, 
 it is extremely important for RTL designers to signoff a good quality RTL 
 to the verification as well as implementation team to ensure that there ar
 e minimal ECOs.\nFor hierarchical SoC, while QoR stub flow or grey box flo
 w comes with accuracy issues, flat has its own challenges with performance
  and signal to noise (SNR)issues.\nTherefore, it becomes mandatory to deve
 lop an abstraction methodology for the RTL checking and Low power verifica
 tion in the SoC design which ensures high quality RTL without any performa
 nce impact.\nThis paper proposes abstraction methodology in the hierarchal
  SoC design which address issues related to IP-SoC handoff by generating t
 he lint abstract model and static abstraction model and validating the abs
 tract model at the SoC level. In this paper, we would discuss about variou
 s advantages and challenges related to Abstraction flow RTL-Lint and RTL-L
 ow power checking in the hierarchical SoC design\n\nVirtual Program: Prese
 nted In-Person
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