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BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:DAC Pavilion
DTSTART;TZID=America/Los_Angeles:20211206T163000
DTEND;TZID=America/Los_Angeles:20211206T173000
UID:dac_DAC 2021_sess260_DESPOST132@linklings.com
SUMMARY:A Low Cost, Scalable and Predictable Gate Level Simulation Methodo
 logy for Giga-Scale SOCs
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nA Low
  Cost, Scalable and Predictable Gate Level Simulation Methodology for Giga
 -Scale SOCs\n\nNaicker\n\nIncreasing time-to-market pressure with short co
 nvergence cycle runway for giga-scale SOCs mandates a GLS methodology that
 ’s cost effective, scalable and predictable. GLS on giga-scale SOCs 
 is costly due to below reasons :-\na. High initial bring-up cost for infr
 astructure and testbench.\nb. Predictability issues with huge monolithic 
 models having capacity and runtime issues.\nc.  Models with no modular de
 bug hooks.\nThe ‘Hybrid GLS’ approach with 'Shadow RTL' method
 ology presented in here addresses these concerns and the results obtained 
 as well as the gains of the approach are shared - as reported from two gen
 erations of giga-scale SOC tapeouts. The methodology presented has success
 fully been applied at IP, Subsystem as well as SOC levels and the qualitat
 ive as well as quantitative gains have been presented.\n\nVirtual Program:
  Presented In-Person
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