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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:DAC Pavilion
DTSTART;TZID=America/Los_Angeles:20211206T163000
DTEND;TZID=America/Los_Angeles:20211206T173000
UID:dac_DAC 2021_sess260_DESPOST135@linklings.com
SUMMARY:Routability Improvement Methodology Using Multiple Standard Cells 
 with Various Pin Location
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nRouta
 bility Improvement Methodology Using Multiple Standard Cells with Various 
 Pin Location\n\nKwon, Kim, Park, Shin, Shin...\n\nWe introduce a new desig
 n method for routability improvement . It can contributes to save routing 
 resource by using direct pin connection with multiple standard cells with 
 various pin location in advanced node suffered by low layer PDN and more d
 ense metal usage for pin shape. The proposed direct low layer connection f
 ocus on reducing routing congestion and detouring for pin routing connecti
 on with ① preparing variant pin cells ② enabling P&R method to
  connect low layer more directly. In this work, we observed that hold fix 
 chain is promising candidate for application and demonstrate variant cell-
 set targeting for hold fixing are efficient to connect pin more directly w
 ithout any performance degradation with industrial test-case. In addition,
  the proposed methods can achieve more than 2% block area scaling using mo
 re direct low layer connection. Future work: we are studying for further p
 erformance improvement by resistance reduction using low layer direct conn
 ection.\n\nVirtual Program: Presented In-Person
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