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DTSTART:19700308T020000
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DTSTART:19701101T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:DAC Pavilion
DTSTART;TZID=America/Los_Angeles:20211206T163000
DTEND;TZID=America/Los_Angeles:20211206T173000
UID:dac_DAC 2021_sess260_DESPOST144@linklings.com
SUMMARY:Towards measuring layout pattern coverage: a Machine Learning Appr
 oach
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nTowar
 ds measuring layout pattern coverage: a Machine Learning Approach\n\nFu\n\
 nDifferent types of layout pattern are used for yield learning. Despite fi
 nding a representative layout pattern is crucial, there is no formal and r
 eliable method to measure the layout pattern coverage. Traditional high di
 mension reduction techniques such as tSNE, SoM (Self organized map) are us
 ed to visualize the pattern space which have the following limitations: 1)
  process is not reversible. 2) could not measure the coverage numerically.
  In this paper, we presented a novel method to measure the pattern coverag
 e based on known product pattern space via squish based layout topology re
 presentation.  The paper covers:\n1)	Review of traditional high dimension 
 reduction techniques for pattern topology space visualization\n2)	Autoenco
 der based ML model for dimension reduction for visualization in discreet l
 atent dimension (using discrete latent dimension vs traditional 2D/3D visu
 alization)\n3)	A convex Hull (minimum bounding box) in latent dimension me
 thod for coverage aggregation\n4)	Layout pattern generation for yield lear
 ning vehicle from space of interest in the latent dimension\n\nML model ar
 chitecture and autoencoder training are presented in detail with a focus o
 n techniques on maintain high fidelity of the encoding and decoding proces
 s. The methodology is applied in the latest advanced node process developm
 ent.\n\nVirtual Program: Presented In-Person
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