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DTSTAMP:20211208T164406Z
LOCATION:DAC Pavilion
DTSTART;TZID=America/Los_Angeles:20211206T163000
DTEND;TZID=America/Los_Angeles:20211206T173000
UID:dac_DAC 2021_sess260_DESPOST163@linklings.com
SUMMARY:Enhanced Analytics and Reporting for Triage and Sign-off Timing
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nEnhan
 ced Analytics and Reporting for Triage and Sign-off Timing\n\nKalafala, Ta
 ggart\n\nDeveloping insights for problems produced by Static Timing Analys
 is (STA) and optimization for high performance microprocessor designs requ
 ires in-depth analysis of both timing and physical data; this is a big dat
 a problem. This task has four main challenges, including: managing design 
 hierarchy, reporting, linking data across time, and providing a reliable a
 nd scalable platform. Our new system extends the Design Data (DD) model us
 ing a hybrid data store architecture and methodology. This system addresse
 s the above challenges for circuit design analysis and debug.\n\nThe DD mo
 del efficiently stores read-only netlist, timing, power, and physical (e.g
 ., placement, congestion, routing) data in a compressed binary file on dis
 k. Furthermore, DD contains the full timing graph enabling efficient path 
 traversal and custom interactive analysis. This binary file is extended wi
 th a timing path-based “hybrid cache data store” using an SQL database and
  custom DD WebSocket server.\n\nDesigners can generate metrics charts to e
 valuate progress and focus efforts over a project’s life cycle. They can c
 ompare past and current data sets to identify and assess specific design t
 rends and failure modes. Designers can define custom rules to categorize, 
 filter, triage, and assign timing paths which need to be fixed, even acros
 s multi-year projects.\n\nVirtual Program: Presented In-Person
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