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BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:DAC Pavilion
DTSTART;TZID=America/Los_Angeles:20211206T163000
DTEND;TZID=America/Los_Angeles:20211206T173000
UID:dac_DAC 2021_sess260_DESPOST185@linklings.com
SUMMARY:A Scalable Multicore RISC-V GPGPU Accelerator for High-End FPGAs
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nA Sca
 lable Multicore RISC-V GPGPU Accelerator for High-End FPGAs\n\nTine, Elsab
 bagh\n\nThe recent generation of high-end FPGAs provide a high computation
 al capability, and energy-efficient makes them attractive in high-performa
 nce computation and architecture research thanks to their reconfigurabilit
 y. Exploring the implementation of a high-bandwidth accelerator on these l
 arge FPGAs presents a unique challenge in how to best utilize the availabl
 e variety of computing resources to achieve the maximum performance. In th
 is work, we implemented Vortex, a full-scale PCIe-based GPGPU accelerator 
 on modern high-end Intel FPGAs. Vortex implements the RISC-V ISA with an e
 xtension to support Single-Instruction Multiple-threads (SIMT) execution m
 odel. Vortex implements a multi-core architecture with high-bandwidth full
 y pipelined non-blocking caches, and a scratchpad shared memory to achieve
  maximum throughput. We leveraged the hardened Integer arithmetic and Floa
 ting-Point DSPs available on the FPGA to achieve maximum computational eff
 iciency. The Vortex platform is highly customizable and scalable with a co
 mplete open-source compiler, driver, and runtime software stack with OpenC
 L support to enable research in GPU architectures. We managed to fit a 16-
  core processor configuration with high-bandwidth caches on Intel Arria10 
 FPGA, clocking at 203-234 MHz, making Vortex a practical framework for GPU
  hardware research.\n\nVirtual Program: Presented In-Person
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