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BEGIN:VEVENT
DTSTAMP:20211208T164406Z
LOCATION:DAC Pavilion
DTSTART;TZID=America/Los_Angeles:20211206T163000
DTEND;TZID=America/Los_Angeles:20211206T173000
UID:dac_DAC 2021_sess260_IPPOST103@linklings.com
SUMMARY:Shift-left Post-Silicon verification with Speed and Accuracy
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nShift
 -left Post-Silicon verification with Speed and Accuracy\n\nMonroy\n\nIn ea
 rly days, Post-silicon validation was crucial before market release to che
 ck the accuracy of any chip and due to early-to-market need, techniques to
  use such methods got easier using simulators support at very initial stag
 es e.g. alpha, beta, early, limited and release of RTL. Simulator support 
 is really helpful to narrow down almost all the bugs in logic path at very
  early stage of verification. But on the other hand, some of the realtime 
 validation techniques are least viable on simulators for e.g. Fault/Defect
  Testing, Functional/Stress validation, hardware/software co-validation an
 d performance validation. One of the examples under the category of Fault/
 Defect testing, DFT verification techniques are widely recognised to unfol
 d design bugs and perform efficient functional verification. But over the 
 past years, design got bigger in size and complex in logic density, which 
 also resulted to increase complexity in test-glue around DUT. Hardware acc
 eleration support on such verification techniques make it fairly easy and 
 faster to do DFT closure with a reduction of months efforts to days. Proto
 typed version of your RTL running on a mega-hertz speed makes it faster an
 d easier enough to re-iterate the whole process of DFT verification.\n\nVi
 rtual Program: Presented In-Person
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