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DTSTAMP:20211208T164512Z
LOCATION:DAC Pavilion
DTSTART;TZID=America/Los_Angeles:20211207T163000
DTEND;TZID=America/Los_Angeles:20211207T173000
UID:dac_DAC 2021_sess261@linklings.com
SUMMARY:Designer, IP, and Embedded Systems Poster Gladiators Presentation
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nThe D
 esigner, IP and Embedded Tracks Poster presentations will be eligible to w
 in the prestigious DAC Gladiator Poster Award.  These selected posters wil
 l present their posters live on Monday-Wednesday from 4 -5 PM in the DAC  
 Pavilion. Winners of the award will be announced and recognized on Wednesd
 ay.\n\nCANCELLED End-to-End Solution for structured implementation of high
 -speed data buses\n\nBehera, Agarwal, Rai, Tuteja\n\nHigh-speed buses requ
 ire multi-stage pipeline repeater flops to travel large distance (> 10mm) 
 in complex SoCs (size > 200mm2). Meeting stiff performance targets (1Ghz+)
  on these bidirectional busses across PVT corners is highly challenging. S
 tandard EDA tools do not offer complete solutions and req...\n\n----------
 -----------\nDeep data for faster silicon bring-up, characterization, and 
 qualification with higher confidence\n\nDatta, Baruch\n\nThe process of re
 aching volume production entails many challenges and uncertainties, especi
 ally as design complexities and process technologies advance. Designers wo
 rk diligently with product engineers to characterize, qualify and validate
  products, while dealing with pressures of time-to-market, pe...\n\n------
 ---------------\nRobust Timing Analysis And Optimization under Parametric 
 On-Chip Process Variation\n\nChai\n\nDesign considering variation is requi
 red in order to maximize profit and improve PPA because variation impact i
 s increased in the deep-sub micron technilogies  The existing POCV method 
 to deal with variation doesn't consider block level timing impact while it
  applies variation impact on each path. I...\n\n---------------------\nExp
 editing Data Converter Layouts using Design Planning & Analysis (DPA) Auto
 mation\n\nThompson, Kumar, Bhargava, LaBorde\n\nHierarchical Designs are c
 hallenging to plan and estimate while layout implementation specially when
  sub-cells layout views are not present throughout the hierarchy. Generate
  All From Source for top cell generates all hierarchical contents flat at 
 top layout view, this becomes very challenging to fl...\n\n---------------
 ------\nInnovative Techniques to Accelerate Error Handling Verification of
  Complex Systems\n\nParikh, Rajendra, Graniello\n\nError handling verifica
 tion is one of the key phases in verification and determining the reliabil
 ity of any embedded system. It involves verifying that the system correctl
 y detected and gracefully reported various errors. This is especially crit
 ical for Smart Network Interface Cards (NICs) (also kno...\n\n------------
 ---------\nAlgorithm to RTL: A Faster Path to Implementation\n\nKlein, Sah
 a\n\nWhen designing hardware, logic designers often need to implement an a
 lgorithm where a reference implementation exists as a software function.  
 High-level Synthesis (HLS) is an approach that converts an algorithm’s C/C
 ++ implementation to a synthesizable hardware description.  However, to ge
 t a good ...\n\n---------------------\nHybrid Emulation Methodology for SS
 D Design\n\nLee\n\nAs SSD design gets more complicated, faster simulation 
 for HW/FW co-verification is heavily required to improve time-to-market. H
 ybrid emulation is a viable solution to achieve the requirement by combini
 ng a virtual platform with an emulator. In this work, we propose a hybrid 
 emulation methodology c...\n\n---------------------\nA flexible SAR-ADC IP
  for multiple technodes\n\nReich, Prautsch, Jotschke\n\nWe present an nove
 l charge-redistribution SAR-ADC, which is featured by covering sampling ra
 tes from 100 Sps up to 2 MSps with high accuracy up to 11 bit ENOB.\nWe ac
 hieve Ultra-low-power consumption down to 2.3 µW @ 10kSps for IoT and medi
 cal applications. The SAR-ADC IP is silicon-proven in various...\n\n\nVirt
 ual Program: Presented In-Person
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