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BEGIN:VEVENT
DTSTAMP:20211208T164408Z
LOCATION:DAC Pavilion
DTSTART;TZID=America/Los_Angeles:20211207T163000
DTEND;TZID=America/Los_Angeles:20211207T173000
UID:dac_DAC 2021_sess261_DESPOST101@linklings.com
SUMMARY:Innovative Techniques to Accelerate Error Handling Verification of
  Complex Systems
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nInnov
 ative Techniques to Accelerate Error Handling Verification of Complex Syst
 ems\n\nParikh, Rajendra, Graniello\n\nError handling verification is one o
 f the key phases in verification and determining the reliability of any em
 bedded system. It involves verifying that the system correctly detected an
 d gracefully reported various errors. This is especially critical for Smar
 t Network Interface Cards (NICs) (also known as Network Accelerators), as 
 they are usually located in an isolated environment and need to be continu
 ously online with little human interaction. In addition, failure to report
  an error may result in security vulnerabilities, resulting in a denial of
  service or other exploits. \nDue to the technology advancement in recent 
 years, the complexity of Smart NICs has increased, resulting in a greater 
 number of error scenarios. This has made the task of error handling verifi
 cation even more challenging using traditional constraint-based random ver
 ification. \nWe leveraged various Formal Property Verification (FPV) techn
 iques including back propagation, design reduction and free variables to a
 ddress challenges associated with key verification aspects of error handli
 ng such as error detection, error reporting and graceful completion. Using
  these techniques, we completed the error handling verification task for t
 he HW Decompression Accelerator IP six weeks before the schedule and with 
 less than half the number of engineers compared to traditional constraint-
 based random verification methodology.\n\nVirtual Program: Presented In-Pe
 rson
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